1. Field
Example embodiments relate to a data transceiver system. More particularly, example embodiments relate to a data transceiver system that can sense and correct an error occurring in a data frame lock process.
2. Description of the Related Art
Semiconductor systems use parallel data interfaces for a data transceiver system between semiconductor devices, for example, a double data rate (DDR) semiconductor memory device and a memory controller. In general, such a data transceiver system uses a common input/output (I/O) port through which data is input/output. A maximum delay time and a phase relation (skew) between signals (data, clock signals, etc.) transmitted through the data transceiver system may be defined in a specification or a standard.
Data transceiver systems of next-generation semiconductor memory devices directly use parallel data interfaces. To support high-speed operation and improve channel efficiency, separate I/O ports are applied. To increase mounting density, multi-chip package (MCP) techniques, etc., may also be employed. However, such separate I/O ports makes defining a phase relation between signals more difficult than when the common I/O port is used. In particular, an error may occur in a data frame lock process that may not be detected.